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ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
17
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, SSTL, and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. If the driver is from another vendor, use their
termination recommendation.
Figure 2A. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 2C. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input
Driven by a 2.5V SSTL Driver
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Zo = 50
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
LVPECL
Differential
Input
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50
Zo = 50
3.3V
R1
50
R2
50
R2
50
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Zo = 60
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
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